As the device becomes thinner, band-to-band-tunneling in off-state of the device may bring about larger gate-induced drain leakage current, which has been one of the issues severely affecting MOSFET and flash memory. GIDL current may induce hot hole injection such that the hole may be trapped in the gate oxidation layer, which may lead to instability of the device and possible punching-through of the gate oxidation layer. Therefore, as the thickness of the oxidation layer decreases, the reliability of the oxidation layer in off-state of the device becomes more important, which has drawn more attention in recent years.
The GIDL may be reduced by conventional techniques. For example, the temperature for forming the gate oxidation layer may be increased to 1000-1100° C. The surface state density of the substrate can be reduced by increasing the oxidation temperature, so as to reduce the GIDL. The gate oxidation layer can be formed by conventional processes including Rapid Thermal Oxidation (RTO) and In-Situ Steam Generation (ISSG). However, the gate oxidation layer formed by RTO may have less uniformity than by oxidation furnace, which may lead to disadvantageous large variation of the threshold voltage of the device. In addition, as the dimension of the device is scaled down to 55 nm process and beyond, the oxidation layer formed by ISSG may have a decreased control for the reduction of the GIDL current.
The GIDL may also be reduced by decreasing the concentration of the Lightly-Doped Drain (LDD) region. As scaling down of device dimension, short channel effects have been an increasingly severe problem. The short channel effects may be suppressed by formation of the LDD. In order to suppresses the short channel effects, the LDD must have a ultra-shallow junction. However, the LDD may have increased concentration so as to avoid reduction of the driving current. If the GIDL current has been decreased by reducing the concentration of the LDD, the resistance of the channel may be increased and the driving current may be reduced, which may deteriorate device performance. Therefore, it is disadvantageous to reduct GIDL current by lowering the concentration of the LDD for future Integrated Circuits (IC) device.
It has been an urgent challenge to be solved for providing a method for manufacturing a MOS transistor with effectively reduced GIDL current.